1. Field of the Invention
The present invention relates to cancellation of DC offset component that is likely to be included in an output signal, more particularly to a receiver used for mobile communication such as cellular phones.
2. Description of Related Art
Mobile communication appliances such as cellular phones rapidly prevailing in recent years need to meet demands on miniaturization, weight saving, and multi-function design. To meet such demands, in place of superheterodyne system conventionally used for a radio processing section, there has been widely employed direct conversion system that does not require an intermediate frequency signal (IF signal) and directly converts a radio frequency signal (RF) into a baseband signal. Since this system does not require a section for processing an IF signal, circuit scale of it can be compressed more than that of the superheterodyne system, which contributes to miniaturization, weight saving, and multi-function design of mobile communication appliance kind.
However, since the direct conversion system directly converts an RF signal into a baseband signal, this system cannot remove unnecessary DC offset components whereas DC offset components in an IF signal were removed by a band-pass filter or the like in the superheterodyne system. Accordingly, the direct conversion system requires a particular circuit for canceling DC offset.
FIG. 8 through FIG. 11 show examples of DC offset cancel circuits conventionally used. Out of those, examples of circuit structure shown in FIG. 8 through FIG. 10 are suitable for communication system such as called FDMA (frequency division multiple access), CDMA (code-division multiple access) or the like. FDMA and CDMA are communication system for receiving RF signals that succeed in terms of time. On the other hand, circuit structure shown in FIG. 11 is suitable for communication system such as called TDMA (time division multiple access) or the like. TDMA is communication system for receiving RF signals that do not succeed in terms of time. In the following descriptions, against TDMA system, communication system for receiving RF signals that succeed in terms of time will be mentioned as non-TDMA system.
It should be noted that FDMA (frequency division multiple access) is communication system that different frequencies are allocated to respective channels and CDMA (code-division multiple access) is communication system that different codes are allocated to respective channels. In both FDMA and CDMA, receiving signals succeed in terms of time. On the other hand, TDMA (time division multiple access) is communication system that channels are allocated to time slots each of which has its predetermined time length and RF signals circulate in each channel. Accordingly, receive operation is conducted in predetermined time slots only.
FIG. 8 shows circuit structure 110 directed to first prior art. In the circuit structure 110, there are provided highpass filters (HPF) 101, and 102 in signal paths that lead to differential output signals OUT, XOUT from differential input signals IN, XIN, respectively, through an amplifier (AMP) 11, whereby DC offset is cancelled. In FIG. 8, the highpass filters (HPF) 101, and 102 are provided at input side and output side of the amplifier (AMP) 11, respectively, whereby DC offset components are cut out in double. Other than this manner of DC offset cancellation, the first prior art can be structured with either one of the highpass filters (HPF). There are structured the highpass filters (HPF) 101, and 102 including capacitor elements in the signal paths, and, on demand, further including resistance elements between output side of the capacitor elements and reference voltage. In the circuit structure 110, DC offset is filtered in a form of analog signal and finally cancelled. Circuit structure as such is suitable for non-TDMA system where signals that succeed in terms of time are dealt.
FIG. 9 shows circuit structure 120 directed to second prior art. In the circuit structure 120, differential output signals OUT, XOUT are integrated by an integration circuit 103 and fedback to differential input signals IN, XIN, whereby DC offset is cancelled. The integration circuit 103 is constituted by a comparator 12 and a time constant circuit that is constituted by connecting two couples of a resistance element and a capacitor element (R101 and C101, R102 and C102) between differential input side and differential output side of the comparator 12. Differential output signals OUT, XOUT inputted through the resistance elements R101 and R102 include AC signal components as AC component and DC offset component as DC component. However, the integration circuit 103 integrates the differential output signals OUT, XOUT depending on time constant determined by the two couples of resistance element and capacitor element (R101 and C101, R102 and C102) and only predetermined DC offset components of those signals are feedback to an amplifier (AMP) 11. Although FIG. 9 shows structure that a feedback signal is directly fedback to differential input signals IN, XIN, it is possible to feedback a feedback signal to a point other than the input signals IN, XIN if it is a point capable of adjusting DC offset components of the amplifier (AMP) 11. For example, a feedback signal can be feedback to a bias current source to an input-stage differential pair of the amplifier (AMP) 11. Circuit structure as such is suitable for non-TDMA system where signals that succeed in term of time are dealt.
It should be noted that the comparator 12 is a circuit that has a predetermined gain and outputs a signal depending on differential signals of differential output signals OUT, XOUT.
FIG. 10 shows circuit structure 130 directed to third prior art. In the circuit structure 130, differential output signals OUT, XOUT are compared at a comparator 12 and differential output signals as comparison result are fedback to an amplifier (AMP) 11 through a lowpass filter constituted by two couples of a resistance element and a capacitor element (R103 and C103, R104 and C104), whereby DC offset is cancelled. The differential output signals OUT, XOUT and the comparison result include signal components as AC component and offset components as DC components. However, only predetermined DC offset components are extracted by the lowpass filter 104 and fedback to the amplifier (AMP) 11. Different from the case of FIG. 9, FIG. 10 is structured such that a feedback signal is feedback to an internal circuit such as bias current source to an input-stage differential pair of the amplifier (AMP) 11. The circuit structure 130 filters analog signals through the lowpass filter 104 and calculates a correction value of DC offset components. Circuit structure as such is suitable for non-TDMA system where signals that succeed in term of time are dealt.
FIG. 11 shows circuit structure 140 directed to fourth prior art. In the circuit structure 140, differential output signals OUT, XOUT are compared at a comparator 12 and then, converted into digital signals by an AD converter 18. To these digital signals, digital processing is applied by a digital signal processing circuit (DSP) so as to output correction signals against DC offset components. Since the correction signal is a digital signal, the signal is converted into an analog signal by a DA converter 17 and fedback to an amplifier (AMP) 11. In case a predetermined time slot in a predetermined communication time cycle is set as offset-quantity detecting time like TDMA system, a correction value obtained by signal processing and calculation is stored in the digital signal processing circuit (DSP) 13 or the DA converter 17, whereby DC offset is cancelled. In the circuit structure 140, an analog signal is converted into a digital signal through signal processing and a correction value and then, a correction value of DC offset component is calculated. Circuit structure as such is suitable for TDMA system where a predetermined time slot in a predetermined communication time cycle is provided as offset-quantity detecting time and a correction value of DC offset components in the next communication time cycle is determined during this predetermined time slot.
Furthermore, as communication system of mobile radio communication appliances, different communication systems actually diversify region by region: PDC, a kind of FDMA, is prevailed in Japan whereas GSM, a kind of TDMA, is prevailed in Europe. Furthermore, there has been raised and considered W-CDMA system as the next generation communication system. Therefore, there is possibility that another different communication system will coexist with the W-CDMA system while a transitional period to the next generation communication system. So, it is considered convenient that a single communication appliance is compatible with pluralities of communication system. Due to demand as such, there have been proposed dual-mode-structured receivers capable of coping with both communication system, namely, TDMA system and non-TDMA system. FIG. 12 specifically shows circuit structure capable of changing over switches of a DC offset cancel circuit. In FIG. 12, selection circuits 105 and 106 change over switches like that in case of TDMA system, the DC offset cancel circuit uses the circuit structure 140, whereas in case of non-TDMA system, the DC offset cancel circuit uses the circuit structures 110 and 120 or 130.
However, the dual-mode-structured DC offset cancel circuit having changeover-circuit structure as shown in FIG. 12 must include both the DC offset cancel circuit 140 suitable for TDMA system and the DC offset cancel circuits 110, 120, or 130 suitable for non-TDMA system. The dual-mode-structured DC offset cancel circuit further requires the selection circuits 105, 105, 106, 106 that control and select between the two types of DC offset cancel circuits and a control circuit (not shown) for outputting control signals. Inclusion of such circuits makes circuit scale large, which is problematic for mobile communication appliances such as cellular phones for which miniaturization and weight saving design are required.
Furthermore, it is conceivable to apply the circuit structure 110 through 130 suitable for non-TDMA system, directed to first through third prior art, to TDMA system. However, for securing propagation of signal components without being cut out in non-TDMA system, only DC offset components must be cut out by setting frequency band of the highpass filters 101 and 102 in the first prior art to sufficiently low frequency. Furthermore, for securing propagation of signal components, only DC offset components must be fedback as correction value in such a manner that time constant of the integration circuit 103 of the second prior art is set sufficiently large or, frequency band of the lowpass filter 104 of the third prior art is set sufficiently low. Any of these countermeasures intends to make a capacitor value of the capacitor elements C101 through C104 sufficiently large. Therefore, in case the circuit structure 110 through 130 are used for TDMA system where a predetermined time slot in a predetermined communication time cycle is allocated to each channel and a signal is received only while the predetermined time slot, rising time of a signal received during a predetermined time slot is likely to be long. Due to long rising time, there is fear that the circuit structure 110 through 130 cannot keep up with high-speed operation, which is problematic.
Vice versa, it is also conceivable to apply the circuit structure 140 suitable for TDMA system, directed to the fourth prior art, to non-TDMA system. However, in TDMA system, a predetermined time slot in a predetermined communication time cycle is allocated to each channel for receiving a signal as well as other predetermined time slot is allocated for offset quantity detection time, and operations of each channel and offset quantity detection are conducted in predetermined time slots allocated for each of them. Therefore, such communication system is hard to apply to non-TDMA system where special time for offset quantity detection cannot be secured. This is problematic.